1. Field of the Invention
The present invention relates to an electro-static discharge (ESD) protection circuit and, more particularly, to an ESD protection circuit with a low snapback voltage that is protected from non-ESD voltage spikes and ripples.
2. Description of the Related Art
A silicon-controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a snapback voltage. When the voltage across the first and second nodes rises to be equal to or greater than the snapback voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the snapback voltage.
As a result of these characteristics, SCRs have been used to provide electro-static discharge (ESD) protection. When used as an ESD protection circuit, the first node becomes a to-be-protected node, and the second node becomes a reference node. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias on the to-be-protected node. The snapback voltage of the SCR is then set to a value that is less than the maximum voltage of the window.
Thus, when the voltage across the to-be-protected node and the reference node is less than the snapback voltage, the SCR provides an open circuit between the to-be-protected node and the reference node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the snapback voltage, such as when an ungrounded human-body contact occurs, the SCR provides a low-resistance current path from the to-be-protected node to the reference node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the reference node.
FIG. 1 shows a cross-sectional view that illustrates a prior-art SCR 100. As shown in FIG. 1, SCR 100 includes a p−semiconductor substrate 110, an n+ buried layer 112 that is formed in the top surface of p− semiconductor substrate 110, and an n− epitaxial layer 114 that is grown on p− semiconductor substrate 110.
SCR 100 also includes an n− well 120, a p− well 122, and a number of shallow trench isolation regions 124 that are formed in n− epitaxial layer 114. In addition, SCR 100 includes an n+ region 130 and an p+ region 132 that are formed in n− well 120, separated by a shallow trench isolation region 124, and electrically connected together and to a to-be-protected node 134. As shown in FIG. 1, p+ region 132 lies closer to p− well 122 than does n+ region 130.
In addition, SCR 100 includes an n+ region 140 and a p+ region 142 that are formed in p− well 122, separated by a shallow trench isolation region 124, and electrically connected together and to a reference node 144. As shown in FIG. 1, n+ region 140 lies closer to n− well 120 than does p+ region 142.
In operation, when the voltage across nodes 134 and 144 is positive and less than the snapback voltage, the voltage reverse biases the junction between n-well 120 and p-well 122. The reverse-biased junction, in turn, blocks charge carriers from flowing from node 134 to node 144. However, when the voltage across nodes 134 and 144 is positive and equal to or greater than the snapback voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into p− well 122, and a large number of electrons to be injected into n− well 120. The increased number of holes increases the potential of p− well 122 in the region that lies adjacent to n+ region 140, and eventually forward biases the junction between p− well 122 and n+ region 140.
When the increased potential forward biases the junction, a npn transistor that utilizes n+ region 140 as the emitter, p− well 122 as the base, and n− well 120 as the collector turns on. When turned on, n+ (emitter) region 140 injects electrons into (base) p− well 122. Most of the injected electrons diffuse through (base) p− well 122 and are swept from (base) p− well 122 into (collector) n-well 120 by the electric field that extends across the junction. The electrons in (collector) n− well 120 are then collected by n+ region 130.
A small number of the electrons injected into (base) p− well 122 recombine with holes in (base) p− well 122 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) p− well 122 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n− well 120 also decrease the potential of n− well 120 in the region that lies adjacent to p+ region 132, and eventually forward bias the junction between p+ region 132 and n− well 120. When the decreased potential forward biases the junction between p+ region 132 and n− well 120, a pnp transistor formed from p+ region 132, n− well 120, and p− well 122 turns on.
When turned on, p+ (emitter) region 132 injects holes into (base) n− well 120. Most of the injected holes diffuse through (base) n− well 120 and are swept from (base) n− well 120 into (collector) p− well 122 by the electric field that extends across the junction. The holes in (collector) p− well 122 are then collected by p+ region 142.
A small number of the holes injected into (base) n− well 120 recombine with electrons in (base) n− well 120 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n− well 120 as a result of the broken-down reverse-biased junction, and n− well 120 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) p− well 122 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 140. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 140 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 132 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
One of the advantages of SCR 100 over other ESD protection devices, such as a grounded-gate MOS transistor, is the double injection provided by n+ region 140 and p+ region 132 of SCR 100. With double injection, SCR 100 provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device, thus increasing the ESD protection capability. (Protection capability can be defined as the required contact width of the structure required to protect from a given ESD pulse amplitude, or the maximum protected ESD pulse amplitude for a given contact width.)
One of the disadvantages of SCR 100, however, is that a very large positive voltage, e.g., 50 volts, must be dropped across nodes 134 and 144 before the junction between n− well 120 and p− well 122 breaks down. As a result, SCR 100 can not be used to protect devices, such as MOS transistors, that can be permanently damaged by much lower voltages, e.g., 15 volts.
One solution to this problem, known as a laterally diffused MOS (LDMOS) SCR, incorporates a high-voltage LDMOS transistor into SCR 100. FIG. 2 shows a cross-sectional view that illustrates a prior art LDMOS SCR 200. LDMOS SCR 200 and SCR 100 are similar and, as a result, utilize the same reference numerals to designate the structures that are common to both devices.
As shown in FIG. 2, LDMOS SCR 200 differs from SCR 100 in that LDMOS SCR 200 includes a channel region 210 of p− well 122, a layer of gate oxide 212 that is formed on epitaxial layer 114, and a gate 214 that is formed on gate oxide layer 210 over channel region 210 and a portion of n− well 120. In addition, gate 214 is connected to reference node 144 via a resistor R.
In operation, LDMOS SCR 200 operates the same as SCR 100 except that gate 214 substantially lowers the snapback voltage. During an ESD event, the voltages on n+ region 130 and n− well 120 rise quickly with respect to the voltage (ground) on p+ region 142 and p− well 122. In addition, n− well 122 is capacitively coupled to gate 214. As a result, the voltage on gate 214 also rises quickly, and turns on the NMOS transistor operation of LDMOS SCR 200.
When the NMOS transistor operation of LDMOS SCR 200 turns on, electrons flow from n+ region 140 to n+ region 130. The rising voltage on n− well 120 along with the flow of electrons into n− well 120 causes the pn junction between n− well 120 and p− well 122 to break down at a much lower snapback voltage than the snapback voltage of SCR 100. Once the pn junction breaks down, LDMOS SCR 200 continues to operate the same as SCR 100.
One problem with LDMOS SCR 200 is that, because of the low snapback voltage, LDMOS SCR 200 is susceptible to improperly turning on in response to non-ESD voltage spikes and ripples. For example, when LDMOS SCR 200 is utilized to ESD protect an input voltage pin (e.g., node 134 is connected to the input voltage pin and node 144 is connected to a ground pin) of a high-voltage switcher, such as a high-voltage buck converter, the high-voltage signals output by the switcher can cause non-ESD voltage spikes and ripples to appear on the input voltage pin of the switcher, and thereby on node 134 of LDMOS SCR 200. Since LDMOS SCR 200 has a relatively low snapback voltage, the non-ESD voltage spikes and ripples on node 134 can cause LDMOS SCR 200 to improperly turn on.
Thus, there is a need for an ESD protection circuit with a low snapback voltage that is protected from non-ESD voltage spikes and ripples.